1. Technical Field
The present invention relates to a wafer unit for testing and a manufacturing method thereof. In particular, the present invention relates to a wafer unit for testing provided with a plurality of test circuits for testing a plurality of semiconductor chips formed on a semiconductor wafer, and to a manufacturing method thereof.
2. Related Art
An apparatus is already known to conduct a test to a semiconductor wafer in which a plurality of semiconductor chips are formed to test acceptability of each semiconductor chip (see Patent Document No. 1 for example). Such an apparatus can have a probe card that can be collectively electrically connected to a plurality of semiconductor chips.
Patent Document No. 1: Japanese Patent Application Publication No. 2002-222839
One method of testing a semiconductor chip uses a BOST circuit. The BOST circuit can be mounted on a probe card. When a test is conducted to a semiconductor wafer, however, a multitude of BOST circuits are required, which are difficult to be implemented on the printed circuit board of the probe card.
So as to solve the mentioned problem, usage of a semiconductor wafer for a probe card is possible. By doing so, the BOST circuits can be formed highly densely by a semiconductor process, which allows a multitude of BOST circuits to be formed on a probe card.
Usage of a semiconductor wafer for a probe card has the following problem. The semiconductor wafer has to be provided with via holes for electrically connecting the front surface and the rear surface of the semiconductor wafer. Here, because the probe card has been provided with BOST circuits, the time required for forming the via holes should be as short as possible so as to reduce the damage onto the BOST circuits. For example, the time required for forming the via holes penetrating through the semiconductor wafer can be reduced by making the semiconductor wafer used as a board of the probe card as thin as possible.
However, when the semiconductor wafer becomes thin, the strength thereof decreases. Generally speaking, a probe card is brought into contact with a chip to be tested at a certain pressure, the decrease in strength of the semiconductor wafer used as the probe card is not desirable. Especially when the plurality of semiconductor chips formed on a wafer to be tested are tested collectively, the probe card has to have a large area, and so the problem incurred by the decrease in strength of a semiconductor wafer becomes more noticeable.